Wikipedia - Instructions per cycle
In computer architecture, instructions per cycle (IPC), commonly called instructions per clock, is one aspect of a processor’s performance: the average number of instructions executed for each clock cycle. It is the multiplicative inverse of cycles per instruction.
While early generations of CPUs carried out all the steps to execute an instruction sequentially, modern CPUs can do many things in parallel. As it is impossible to just keep doubling the speed of the clock, instruction pipelining and superscalar processor design have evolved so CPUs can use a variety of execution units in parallel – looking ahead through the incoming instructions in order to optimise them.
It seems:
Wikipedia - Cycles per instruction
They are mathematical inverses:
IPC = 1 / CPII searched for ICP/CPI of Apple, Intel, or NVIDIA chips, but they don’t seem to disclose the metrics. I think I should consider CPI/IPC as theoretical models or analytical tools, not as fixed values for modern CPUs (as they can vary drastically depending on instructions or workload).
Wikipedia - Reduced instruction set computer
It’s been 5 (or more years) since I saw the word “RISC” in college. I know I should not use Wikipedia as a reference, but pardon me for now.
From what I digested…
RISC is a CPU architecture style that strives to simplify the instruction set so processors can run faster and more efficiently. Modern performance gains in Apple’s M-series and most mobile processors come from this philosophy.
Wikipedia - Classic RISC pipeline
RISC’s simplicity of instructions made the 5-stage pipeline feasible and efficient.
Classic RISC pipeline has 5 stages, and stages from different instructions can overhap. A single instruction requires 5 stages (cycles) to complete (latency), but because instructions can overlap, CPU can complete one instruction per cycle (throughput). (Please refer to the diagram on the Wikipedia page or other places; it can provide visual understanding.)
TODO: